The 74HC109 is a dual positive edge triggered JK flip-flop featuring individual nJ and nK inputs. It has clock (nCP) inputs, set (nSD) and reset (nRD) inputs and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The nJ and nK inputs control the state changes of the flip-flops as described in the mode select function table. The nJ and nK inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The JK design allows operation as a D-type flip-flop by connecting the nJ and nK inputs together. Inputs include clamp diodes. It enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
- Input levels:
- For 74HC109: CMOS level
- For 74HCT109: TTL level
- J and K inputs for easy D-type flip-flop
- Toggle flip-flop or “do nothing” mode
- Specified in compliance with JEDEC standard no. 7A
- ESD protection:
- HBM JESD22-A114F exceeds 2000 V
- MM JESD22-A115-A exceeds 200 V
- Multiple package options
- Specified from -40 °C to +85 °C and from -40 °C to +125 °C
|IIK||Input Clamping Current||±20||mA|
|IOK||Output Clamping Current||±20||mA|
|Ptot||Total Power Dissipation||500||mW|
* product image for illustration purposes only. actual product may vary.