The 74LS109 devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K and tying J high. They also can perform as D-type flip-flops if J and K are tied together. The 74LS109 is characterized for operation from 0°C to 70°C. The feature of 74LS109 is a package Options Include Plastic “Small Outline” Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs
Specifications:-
| Parameter | Specification |
| Part number | 74LS109 |
| Technology Family | LS |
| VCC (Min) (V) | 4.75 |
| VCC (Max) (V) | 5.25 |
| Bits (#) | 2 |
| Voltage (Nom) (V) | 5 |
| F @ nom voltage (Max) (MHz) | 35 |
| ICC @ nom voltage (Max)(mA) | 15 |
| tpd @ nom Voltage (Max) (ns) | 35 |
| IOL (Max) (mA) | 8 |
| IOH (Max) (mA) | -0.4 |
| Rating | See Data Sheet |
* product image for illustration purposes only. actual product may vary.
Reviews
There are no reviews yet