74LS73 Dual JK Flip Flop with Clear IC (7473) DIP 14 Package

74LS73 Dual JK Flip Flop with Clear IC (7473) DIP 14 Package

The 74LS73 is a Dual JK Flip-Flop with Clear from the 74LS (Low Power Schottky TTL) logic family.
It contains two independent JK flip-flops, each with asynchronous clear inputs.

Each flip-flop changes output state (toggles) on the falling edge of the clock signal when both J and K inputs are HIGH.
When the clear input is LOW, the flip-flop is reset, regardless of the clock or J/K inputs.

This IC is commonly used in frequency division, counters, toggle circuits, and sequential logic designs.

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Features:- 

• • Two Independent Negative Edge Triggered JK Flip-Flops
• • Clear Input Resets the Output
• • Fast Switching Times
• • Operating Temperature up to 70°C
• • Standard TTL Switching Voltages

Specifications:-

Functional Description

The 74LS73 consists of two JK flip-flops, each functioning independently:

• The Clear (CLR) input resets the flip-flop asynchronously (active LOW).
• When CLR = HIGH, the flip-flop responds to the falling edge of the clock:
• If J = K = LOW, the output remains unchanged.
• If J = HIGH, K = LOW, the flip-flop is SET.
• If J = LOW, K = HIGH, it is RESET.
• If J = K = HIGH, the output toggles on each clock pulse.

Applications

• Frequency dividers / Counters
• Toggle flip-flop circuits
• Data storage elements
• Sequential logic design
• Control systems and digital timing
• Divide-by-2 and divide-by-N frequency circuits

74ls73-ic-datasheet