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74LS73 Dual JK Flip-Flop with Clear IC (7473 IC) DIP-14 Package

49.00 + GST

Availability: In stock

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The 74LS73 device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the transition time of the negative going edge of the clock pulse. The data on the J and K inputs is allowed to change while the clock is HIGH or LOW without affecting the outputs as long as setup and hold times are not violated. A low logic level on the clear input will reset the outputs regardless of the levels of the other inputs.


• Two Independent Negative Edge Triggered JK Flip-Flops

• Clear Input Resets the Output

• Fast Switching Times

• Operating Temperature up to 70°C

• Standard TTL Switching Voltages


Parameter Specification
Supply Voltage (VCC) 7 V
Input Voltage (VI) 7 V
Operating free-air temperature range 0°C to +70°C
Storage temperature range –65°C to +150°C


* product image for illustration purposes only. actual product may vary.


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