The 74LS73 contain two independent J-K flip-flops with individual J-K, clock, and direct clear inputs. The 74LS73 is a positive pulse-triggered flip-flops. input is loaded into the master while the clock is high and transferred to the slave on the high-to-low transition. For these devices the J and K inputs must be stable while the clock is high. The 74LS73 contains two independent negative- edge-triggered flip-flops. The J and K inputs must be stable one setup time prior to the high- to-low clock transition for predictable operation. When the clear is low, it overrides the clock and data inputs forcing the Q output low and the output high. The 74LS73 is characterized for operation from O° C to 70° C.
Specification:-
| Symbol | Parameter | Min | Type | Max | Units |
| VCC | Supply Voltage | 4.5 | 5 | 5.25 | V |
| TA | Operating Ambient Temperature Range | 0 | 70 | °C | |
| IOH | Output Current — High | –0.4 | m A | ||
| IOL | Output Current — Low | 8 | m A |
* product image for illustration purposes only. actual product may vary.
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