74LS173 4 bit D type Registers with 3 State Output IC (74173) DIP 16 Package

74LS173 4 bit D type Registers with 3 State Output IC (74173) DIP 16 Package

The 74LS173 is a quad (4-bit) D-type register with 3-state outputs and control features such as parallel load, clock enable, and output enable. It is part of the 74LS TTL (Low Power Schottky) logic family.

This IC is designed to store and transfer 4 bits of data under control of a clock signal. Data on the input lines (D0–D3) is latched into the register on the rising edge of the clock (CLK) when the clock enable inputs (G1 and G2) are LOW.
The outputs (Q0–Q3) can be enabled or placed in high-impedance (Hi-Z) state using the output control inputs (OE1 and OE2), allowing easy bus interfacing.

The 74LS173 provides fast switching speeds, high noise immunity, and low power consumption, making it ideal for use in microprocessor systems, data storage, and bus-oriented applications.

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Features:-

• • 3-State Outputs Interface Directly With System Bus
• • Gated Output-Control LInes for Enabling or Disabling the Outputs
• • Fully Independent Clock Virtually Eliminates Restrictions for Operating in One of Two Modes: – Parallel Load – Do Nothing (Hold)
• • For Application as Bus Buffer Registers
• • Package Options Include Plastic Small-Outline (D) Packages, Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J)

Specifications:-

Functional Description

• Data at D0–D3 is loaded into the register on the rising edge of the clock (CP) only when both enables G1 and G2 are LOW.
• When either G1 or G2 is HIGH, the register retains its previous data (no change).
• When MR (Master Reset) is LOW, all outputs are cleared to 0 asynchronously.
• The output enable inputs (OE1, OE2) control the state of Q0–Q3 outputs:
• When both OE1 and OE2 are LOW, outputs are active.
• When either OE1 or OE2 is HIGH, outputs go to high-impedance (Hi-Z).

Applications

• Microprocessor data latching and buffering
• Bus-oriented systems (with tri-state outputs)
• Parallel data storage / transfer
• Shift register expansion
• Memory data register
• Temporary data holding in digital systems
• I/O port register or latch
• Control and status register implementation

74ls173-ic-datasheet