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74 Series Dip IC
74LS109 Dual J K Positive Edge Triggered Flip Flop IC (74109) DIP 16 Package
₹46.80 (incl. tax)
74LS109 Dual J K Positive Edge Triggered Flip Flop IC (74109) DIP 16 Package
The 74LS109 is a Dual J-K Positive Edge-Triggered Flip-Flop IC from the 74LS (Low Power Schottky TTL) logic family.
It contains two independent J-K flip-flops, each featuring:
- Asynchronous Set (Preset) and Clear (Reset) inputs
- Complementary outputs (Q and Q?)
- Positive-edge triggering, meaning the flip-flop changes state on the rising edge of the clock input.
The device is widely used in digital counters, shift registers, and memory storage applications where toggle or binary state storage is needed.
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Specifications:-
| Parameter | Specification |
| Part number | 74LS109 |
| Technology Family | LS |
| VCC (Min) (V) | 4.75 |
| VCC (Max) (V) | 5.25 |
| Bits (#) | 2 |
| Voltage (Nom) (V) | 5 |
| F @ nom voltage (Max) (MHz) | 35 |
| ICC @ nom voltage (Max)(mA) | 15 |
| tpd @ nom Voltage (Max) (ns) | 35 |
| IOL (Max) (mA) | 8 |
| IOH (Max) (mA) | -0.4 |
| Rating | See Data Sheet |
Applications
- Binary Counters / Frequency Dividers
- Toggle and T Flip-Flop Configuration
- Shift Registers
- Data Storage and Transfer Circuits
- Control Logic Circuits
- Sequential Logic Design
- Pulse Synchronization
- Clocked State Machines
* Product image for illustration purposes only, actual product may vary.
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