The 74595 consists of an 8−bit shift register and an 8−bit D−type latch with three−state parallel outputs. The shift register accepts serial data and provides a serial output. The shift register also provides parallel data to the 8−bit latch. The shift register and latch have independent clock inputs. This device also has an asynchronous reset for the shift register. The 74595 directly interfaces with the SPI serial data port on CMOS MPUs and MCUs.
- Output Drive Capability: 15 LSTTL Loads
- Outputs Directly Interface to CMOS, NMOS, and TTL
- Operating Voltage Range: 2.0 to 6.0 V
- Low Input Current: 1.0 A
- High Noise Immunity Characteristic of CMOS Devices
- In Compliance with the Requirements Defined by JEDEC Standard No. 7A
- ESD Performance: HBM 2000 V; Machine Model 200 V
- Chip Complexity: 328 FETs or 82 Equivalent Gates
- These are Pb−Free Devices
|VCC||Supply Voltage||– 0.5 to + 7.0||V|
|Vin||Input voltage||– 0.5 to VCC + 0.5||V|
|Vout||Output Voltage||– 0.5 to VCC + 0.5||V|
* product image for illustration purposes only. actual product may vary.